Univerzitet "Sv. Kiril i Metodij"

Prirodno-matemati~ki Fakultet-Skopje

Institut za Informatika

DIPLOMSKA RABOTA

POST - RISC PROCESORSKA ARHITEKTURA

izrabotil: Ivan Trpkov

mentor: d-r Marjan Gu{ev

Skopje, fevruari 1997

REZIME

Sega{nata generacija procesori opredeluva edna vozbudliva i nova era na procesori so mnogu visoki performansi. Momentnata generacija na procesori go zadr`uva trendot na rapiden razvoj. Vakov brz razvoj ne e zabele`an od kasnite 80-ti, koga se pojavuvaat RISC procesorite. Ovie procesori imaat golem broj na sli~nosti: reducirano instrukcisko mno`estvo, fiksen instrukciski format, prote~no izveduvawe na instrukcii i dr. Podobruvaweto na performansite se dobiva so odredeni izmeni na procesorskata arhitektura. Ovie izmeni ne mo`at da se karakteriziraat kako RISC implementacii. Novata generacija procesori koja gi realizira ovie izmeni se narekuva post-RISC generacija. Vo tretoto poglavje e napraven pregled na 7 sovremeni procesori koi gi implementiraat principite na post-RISC arhitekturata.

Post-RISC procesorite se razlikuvaat od superskalarnite RISC procesori so zgolemuvawe na instrukciskoto mno`estvo so FISC instrukcii i poaktivno koristewe na hardver za dinami~ko izveduvawe na prerasporeduvaweto na instrukciite. Novi elementi vo post-RISC implementacijata se: edinica za pred-dekodirawe, koristewe na preimenuvani registri za otstranuvawe na izleznite zavisnosti i anti-zavisnostite, bafer za prerasporeduvawe na instrukciite i edinica za kompletirawe.

ABSTRACT

The current generation of processors introduces an exciting new era of high performance processors. These processors uniformly show dramatic increases in performance of a scale which has not been seen since the late 1980s when RISC processors first became available. The RISC processors has a several similarity: reduced instruction set, fixed instruction format, pipelined instruction execution etc.

The performance gains of the current generation are due to changes that are decidedly not-RISC. This current generation of processors are named post-RISC. In the 3 chapter we survey seven processors of the current generation which highlight the principles of post-RISC.The post-RISC generation is distinguished from superscalar RISC processors in several ways. First, the instruction set architecture was further augmented. This trend in ISA is called "Fast Instruction Set Computers" or FISC. Post-RISC processors are much more aggressive at issuing instruction using hardware to dinamically perform the instruction reordering. The new components in a post-RISC implementation include: a predecode unit, the use of rename registers to remove output and anti-dependencies, an instruction reorder buffer and a retire unit.

SODR@INA

VOVED

1 RISC PROCESORI

1.1 RISC KARAKTERISTIKI

1.2 MEMORISKA LATENTNOST

1.3 ZAVISNOSTI I KONFLIKTI

2 POST-RISC PROCESORI

2.1 POST-RISC KARAKTERISTIKI

2.2 ARHITEKTURA NA POST-RISC PROCESOR

2.3 SPOREDBA SO DATAFLOW ARHITEKTURI

3 PREGLED NA POST-RISC PROCESORI

3.1 DEC Alpha 21164

3.2 DEC Alpha 21264

3.3 SUN UltraSPARC-II

3.4 IBM PowerPC 604

3.5 MIPS R10000

3.6 HP PA-8000

3.7 Intel P6

4 ZAKLU^OK

LITERATURA