Links to papers

Western Research Laboratory Digital - Research Reports
http://www.research.digital.com/wrl

Western Research Laboratory Digital - Technical Notes
http://www.research.digital.com/wrl

University of Washington, Seattle - Technical Reports
http://www.cs.washington.edu

Universitat Politecnica de Catalunya, Barcelona - Technical Reports
http://www.ac.upc.es/hpc

University of Wisconsin, Madison - Technical Reports
http://www.cs.wisc.edu/

University of Virginia - Technical Reports
http://www.

Clemson University - Technical Reports
http://www.
Title	*Authors*	*Date*	*Published*
PEWs: A Decentralized Dynamic Scheduler for ILP Processing	Gregory A. Kemp Manoj Franklin		f.pews

University of California - Santa Barbara - Technical Reports
http://www.cs.usb.edu
Title	*Authors*	*Date*	*Published*
A Quantitative Determination of the Optimal Combination of Dynamic Branch Prediction Components	Adam R. Talcott Roger C. Wood Mario Nemirovsky		ECE TR 94-15

University of Michigan - Technical Reports
http://www.cs.umich.edu
Title	*Authors*	*Date*	*Published*
Hardware Support for Hidding Cache Latency	Michael Golden Trevor N. Mudge	1993	CS-TR 152-93
Limited Dual Path Execution	Gary Tyson Kelsey Lick Matthew Farrens	1997	tech97
Wrong-Path Instruction Prefetching	Jim Pierce Trevor Mudge	1994	CSE-TR-222-94
Limits to Branch Prediction	Trevor N. Mudge I-Cheng K. Chen John T. Coffey	1996	CSE-TR-282-96
The Impact of Instruction Compression on I-cache Performance	Trevor N. Mudge I-Cheng K. Chen Peter L. Bird	1997	CSE-TR-330-97


Stanford University
Title	*Authors*	*Date*	*Published*
Limits on Multiple Instruction Issue	Michael D. Smith, Mike Johnson, and Mark A. Horowitz	1989	asplos89_TR
Efficient Superscalar Performance Through Boosting	Michael D. Smith, Mark Horowitz, Monica S. Lam	1992	asplos92
Boosting Beyond Static Scheduling in a Superscalar Processor	Michael D. Smith, Monica S. Lam, and Mark A. Horowitz	1990	isca90_TR
Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors	Mark Horowitz Margaret Martonosi Todd C. Mowry Michael D. Smith	1996	isca96-imem
Effectivness of Data Dependence Analysis	Dror E. Maydan John L. Hennessy Monica S. Lam	1992
Efficient and Exact Data Dependence Analysis	Dror E. Maydan John L. Hennessy Monica S. Lam	1991


University of Illinois
Title	*Authors*	*Date*	*Published*
The Effect of Code Expanding Optimizations on Instruction Cache Design	William Y. Chen Pohua P. Chang Thomas M. Conte Wenmei W. Hwu	1992	IEEE Trans. Computers Vol.42, No.9, Sep.1993, pp.1045-1057
Three Superblock Scheduling Models for Superscalar and Superpipelined Processors	Pohua P. Chang Nancy J. Warter Scott A. Mahlke William Y. Cheng Wen-mei W. Hwu	1991	crhc-91-29
Compiler Technology for Future Microprocessors	Wen-mei W. Hwu Richard E. Hank David M. Gallagher Scott A. Mahlke Daniel M. Lavery Grant E. Haab John C. Gyllenhaal David I. August	1995
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors	Pohua P. Chang Daniel M. Lavery Wen-mei W. Hwu	1991	crhc-91-18
Run-time Cache Hierarchy Managament via Reference Analysis	Teresa L. Johnson Wen-mei W. Hwu	1996	impact-96-01
Run-time Spatial Locality Detection and Optimization	Teresa L. Johnson Matyhew C. Merten Wen-mei W. Hwu	1997	IMPACT-97-02

IEEE MICRO 24 Proceedings, 1991
http://
Title	*Authors*	*Date*	*Published*
Data Access Microarchitecture for Superscalar Processors with Compiler-Assisted Data Prefetching	William Y. Chen Scott A. Mahlke Pohua P. Chang Wen-mei W. Hwu	1991

IEEE MICRO 25 Proceedings, Portland, Oregon, December 1992
http://
Title	*Authors*	*Date*	*Published*
Tradeoffs in Processor/Memory Interfaces for Superscalar Processors	Thomas M. Conte	1992
Code Scheduling for VLIW/Superscalar Processors with Limited Register Files	Tokuzo Kiyohara John C. Gyllenhaal	1992
Stride Directed Prefetching in Scalar Processors	W.C.Fu J.H.Patel B.L.Janssens		pp.102-110 - HC

IEEE MICRO 26 Proceedings, 1993
http://
Title	*Authors*	*Date*	*Published*
Speculative Execution Exception Recovery using Write-back Suppression	Scott A. Mahlke Wen-mei W. Hwu Roger A. Bringmann Richard E. Hank John C. Gyllenhaal	1993
Superblock Formation Using Static Program Analysis	Scott A. Mahlke Wen-mei W. Hwu Roger A. Bringmann Richard E. Hank John C. Gyllenhaal	1993

IEEE MICRO 27 Proceedings, 1994
http://
Title	*Authors*	*Date*	*Published*
A Fill-Unit Approach to Multiple Instruction Issue	Manoj Franklin Mark Smotherman	1994
A HighPerformance Microarchitecture with HardwareProgrammable Functional Units	Rahul Razdan Michael D. Smith	1994	micro94
Data Relocation and Prefetching for Programs with Large Data Sets	Yoji Yamada John Gyllenhaal Grant Haab Wen-mei Hwu	1994
The Anatomy of Register File in a Multiscalar Processor	Scott E.Breach T. N. Vijaykumar Gurindar S.Sohi	1994

IEEE MICRO 28 Proceedings, Dec.1-3,1995
http://american.cs.ucdavis.edu/Micro28/html/finalprogram.html
Title	*Authors*	*Date*	*Published*
Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency	T. M. Austin G. S. Sohi	1995
Improving CISC Instruction Decoding Performance Using a Fill Unit	Mark Smotherman Manoj Franklin	1995
Dynamic Rescheduling: A Technique for Object Code Compatibility in VLIW Architectures	Thomas M. Conte Sumedh W. Sathaye	1995
A Modified Approach to Data Cache Management	Matthew Farrens Gary Tyson John Matthews Andrew R. Pleszkun	1995
Performance issues in Correlated Branch Prediction Schemes	Nicolas Gloy Michael D. Smith Cliff Young	1995	also in Proc. 28th Annual ACM/IE3 Intl. Symp. & Workshop on MicroArhcit. Nov. 1995
Decopuling Integer Execution in Superscalar Processors	Subbarao Palacharla J. E. Smith	1995
Region-Based Compilation: An Introduction and Motivation	Richard E.Hank Wen-mei Hwu B.Ramakrishna Rau	1995

IEEE MICRO 29 Proceedings, 1996
http://
Title	*Authors*	*Date*	*Published*
Optimization of Machine Description for Efficient Use	John Gyllenhaal Wen-mei Hwu B. Ramakrishna Rau	1996
The Performance Potential of Data Dependence Speculation & Collapsing	Yiannakis Sazeides Stamatis Vassiliadis	1996
Trace Cache a Low Latency Approach to High Bandwidth Instruction Fetching	Eric Rotenberg Steve Bennett James E. Smith	1996
Exceeding the Dataflow Limit via Value Prediction	Mikko H.Lipasti John Paul Shen	Dec. 1996	Proceedings of 29th Annual ACM/IEEE Int. Symposium and Workshop on Microarchitecture, pp.226-237 - HC

IEEE MICRO 30 Proceedings, Dec.1-3,1997
http://www.ece.ncsu.edu/micro30/ap30.htm
Title	*Authors*	*Date*	*Published*
Can Program Profiling Support Value Prediction	Freddy Gabbay Avi Mendelson	12/97
The Predictability of Data Values	Yiannakis Sazeides James E.Smith	12/97
Exploiting Dead Value Information	Milo M. Martin Amir Roth Charles N.Fisher	12/97
Reducing the Performance Impact of Instruction Cache Misses by Writing Instructions into the Reservation Stations Out-of-Order	Jared Stark Paul Racunas Yale N. Patt	12/97	Proceedings of Micro-30
Streamlining Inter-operation Memory Communication via Data Dependence Prediction ! additional figures for section 3!	Andreas Moshovos Gurindar S. Sohi	12/97
Run-time Spatial Locality Detection and Optimization	Teresa L. Johnson Matthew C. Merten Wen-mei W. Hwu	12/97
The Multicluster Architecture: Reducing Cycle Time Through Partitioning	Keith I. Farcas Paul Chow Norman P. Jouppi Zvonko Vranesic	12/97

19^th ISCA Int Symposium on Computer Architecture, May,1992
http://
Title	*Authors*	*Date*	*Published*
Dynamic Dependency Analysis of Ordinary Programs,	Todd M. Austin Gurindar S. Sohi	1992	Proceedings
Limits of Control Flow on Paralelism	Monica S. Lam Robert P. Wilson	1992	Proceedings
Alternative Implemenations of two-level Adaptive Branch Prediction	T.Y.Yeh Y.N.Patt	1992	Proceedings of 19th Int. Symposium on Computer Architecture (ISCA) pp.124-134, May 1992

21^st ISCA Int Symposium on Computer Architecture, April,1994 Chicago, IL

Title	*Authors*	*Date*	*Published*
The Impact of Unresolved Branches on Branch Prediction Scheme Performance	Adam R. Talcott Wayne Yamamoto Mauricio J. Serrano Roger C. Wood Mario Nemirovsky	1994	Proceedings pp.12-21
Speculative Disambiguation: A Compiltaion Technique for Dynamic Memory Disambiguation	Andrew Huang Gert Slavenburg John Paul Shen	1994	Proceedings of the 21st Int. Symposium on Computer Architecture, (ISCA) Chicago, IL, April 1994, pp.200-210

22^nd ISCA Int Symposium on Computer Architecture, May,1995

Title	*Authors*	*Date*	*Published*
Streamlining Data Cache Access with Fast Address Calculation	T. M. Austin D. N. Pnevmatikatos G. S. Sohi	1995

23^rd ISCA Int Symposium on Computer Architecture, May,1996

Title	*Authors*	*Date*	*Published*
High-Bandwidth Address Translation for Multiple-Issue Processors	T. M. Austin G. S. Sohi	1996

8th ISCA Int Symposium on Computer Architecture, May,1986

Title	*Authors*	*Date*	*Published*
A Study of Branch Prediction Strategies	James E. Smith	1986	Proceedings of Eighth Annual Symposium on Computer Architecture (ISCA) pp.135-148. Published as Computer News 9 (3), 1986.

24^th ISCA Int Symposium on Computer Architecture, June,1997
http://american.cs.ucdavis.edu/ISCA97
Title	*Authors*	*Date*	*Published*
Dynamic Instruction Reuse	Avinash Sodani Gurindar S.Sohi	06/97
Dynamic Speculation and Synchronisation of Data Dependences	Andreas Moshovos Scott E.Breach T. N. Vijaykumar Gurindar S.Sohi	06/97

25^th ISCA Int Symposium on Computer Architecture, June,1998
http://american.cs.ucdavis.edu/ISCA98 ????
Title	*Authors*	*Date*	*Published*
The Effect of Instruction Fetch Bandwidth on Value Prediction	Freddy Gabbay and Avi Mendelson	1998

7^th ASPLOS ACM Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, Oct 1-5, 1996.
http://www.cag.lcs.mit.edu/asplos7/program
Title	*Authors*	*Date*	*Published*
Value Locality and Load Value Prediction	Mikko H. Lipasti Christopher B. Wilkerson John Paul Shen	1996	Proceedings
CompilerBased Prefetching for Recursive Data Structures	ChiKeung Luk Todd C. Mowry	1996	Proceedings
Analysis of Branch Prediction via Data Compression	I-Cheng K. Chen John T.Coffey Trevor Mudge	1996	Proceedings

6^th ASPLOS ACM Conference on Architectural Support for Programming Languages and Operating Systems, 1994.
http://www.cag.lcs.mit.edu/asplos7/program
Title	*Authors*	*Date*	*Published*
Dynamic Memory Disambiguation Using the Memory Conflict Buffer	David M. Gallagher William Y. Chen Scott A. Mahlke John C. Gyllenhaal Wenmei W. Hwu	1994	Proceedings

5^th ASPLOS ACM Conference on Architectural Support for Programming Languages and Operating Systems 1992.
http://www.
Title	*Authors*	*Date*	*Published*
Sentinel Scheduling for VLIW and Superscalar Processors	Scott A.Mahlke William Y.Chen Wen-mei W. Hwu B.Ramakrishna Rau Michael S.Schlansker	1992	Proceedings

ILP
various
Title	*Authors*	*Date*	*Published*
Advanced Performance Features of the 64-bit PA-8000	Doug Hount	1995	Proc. CompCon pp.123-128
Minimizing Register Requirements under Resource-Constrained Rate-Optimal Software Pipelining	R. Govindarajan Erick R. Altman Guang R. Gao
Informing Loads: Enabling Software to Observe and React to Memory Behaviour	Mark Horowitz Margaret Martonosi Todd S. Mowry Michael D. Smith	1995	TR 95-673
Performance of the strucured Memory Access SMA architecture	G.S.Sohi, E.S.Davidson	August 1984	Proc. 1984 Int. Conf. On Parallel Processing, pp.506-513, Bellaire, MI HC
The use of Intermediate Memories for Low Latency Memory Access in Supercomputer Scalar Units	G.Sohi W.C.Hsu	1990	The Journal of Supercomputing vol.4, pp.5-21 HC
A forward-looking method of Cache Memory Control	J.K. Iliffe	?	? HC

IEEE Proceedings & Transactions & Computer
http://www.cs.wisc.edu/
Title	*Authors*	*Date*	*Published*
The Microachitecture of Superscalar Processors	James E. Smith Gurindar S. Sohi	Dec. 1995	Proceedings of the IEEE
Changing Interaction of Compiler and Architecture	Sarita V.Adve Doug Bourger Rudolf Eigenmann Alasdair Rawsthorn Michael D. Smith Katrine H. Gebotys Mahmood T.Kendemir David J.Lilja Alok N. Choudhary Jesse Z. Funk Penn-Chung Yew	1997	IEEE Computer Dec.1997 pp.51-58
Branch Prediction Strategies and Branch Target Buffer Design	Johny K.F.Lee Alan J.Smith	1984	IEEE Computer vol.17, pp.6-22, Jan. 1984

Detection and Parallel Execution of Parallel Instructions	G.S.Tjaden M.J.Flynn	1970	IEEE Transactions on Computers, C-19 (10), pp.889-895, Oct.1970
Measuring the Parallelism Available for Very Long Instruction Word Architectures	Alexandru Nicolau Joseph Fisher	1984	IEEE Transaction on Computers, C-33, 11, pp.968-976, Nov.1984
Implementing Precise Interrupts in Pipelined Processors,	James E.Smith Andrew R.Pleszkun	1988	IEEE Transactions on Computers, vol.37, 5, pp.562-573, May 1988
Measuring Parallelism in Computation-Intensive Scientific/Engineering Application	Manoj Kumar	1988	IEEE Transaction on Computers, C-37, 9, pp.1088-1098, Sep.1988
Run Time Disambiguation: Coping with Statically Unpredictalble Dependencies	Alexandru Nicolau	1989	IEEE Transactions on Computers, C-38, 5, pp.663-678, May 1989
Efficient Instruction Sequencing with Inline Target Insertion	Wen-mei Hwu Pohua Chang	1992	IEEE Transactions on Computers,
Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring	Michael A.Schuette John P. Shen	1994	IEEE Transactions on Computers, vol.43, No.2 pp.129-140
Instruction Window Size Trade-Offs and Characterization of Program Parallelism	Pradeep K.Dubey George B.Adams III Michael J. Flynn	1994	IEEE Transactions on Computers, vol.43, No.4 pp.431-442
ARB: A Hardware Mechanism for Dynamic Reordering of Memory References (ARB: A Hardware Mechanism for Dynamic Memory Disambiguation)	Manoj Frankiln Gurindar S. Sohi	May 1996	IEEE Transactions on Computers, Vol. 45, No. 5, pp. 552-571,
Decoupled Sectored Caches	Andre Seznec	1997	IEEE Transactions on Computers, vol.46, No.2, pp.210-214
AMMULET-1: An Asynchronios ARM Microrpocessor	J.W. Woods P.Day S.B. Furber J.D.Garside N.C. Paver S.Temple	1997	IEEE Transactions on Computers, vol.46, No.4 pp.385-398
Improving the Accuracy of History Based Branch Prediction	David R. Kaeli Philip G. Emma	1997	IEEE Transactions on Computers, vol.46, No.4 pp.469-472
Partial Resolution in Branch Target Buffers	Barry Fagin	1997	IEEE Transactions on Computers, vol.46, No.10 pp.1142-1145
Multithreading With Distributed Functional Units	Bernard K. Gunther	1997	IEEE Transactions on Computers, vol.46, No.4 pp.399-411
Reducing Memory Penalties by a Programmable Prefetch Engine for On-chip Caches	Tien-Fu Chen	1997	Microprocesors & Microsystems no.21, pp.121-130

IBM Journal of Research and Development
http://www.cs.wisc.edu/
Title	*Authors*	*Date*	*Published*
Understanding Some Simple Processor Performance Limits	P. G. Emma	1997	Vol.41, No.3
Simulation/evaluation Enviroment for VLIW Processor Architecture	J.H.Moreno M.Moudgill K.Ebcioglu E.Altman C.B.Hall R.Miranda S-K.Chen A.Polyak	1997	Vol.41, No.3
Prefetching and Memory System Behavior of the Spec95 Benchmark Suite	M.J.Charney T.R.Puzak	1997	Vol.41, No.3

4^th International Conference on High Performance Computing, 12/97, Cambridge, Massachusetts, USA
http://www.
Title	*Authors*	*Date*	*Published*
Virtual Registers	Antonio Gonzales Mateo Valero Jose Gonzales Teresa Monreal
A Differen Approach to High Performance Computing	Henk Corporaal	-\|\|-	-\|\|-
Applying Time Warp to CPU Design	Murray W. Pearson Richard H. Littin J.A. David McWha John G. Cleary	-\|\|-	-\|\|-
Simultaneous Multithreaded Vector Architecture: Merging ILP and DLP for high performance * Ne e ispe~ateno *	Roger Espasa Mateo Valero	-\|\|-	-\|\|-
Highly Accurate Data Value Prediction * Ne e dobro ispe~ateno	Kai Wang Manoj Franklin	-\|\|-	-\|\|-
Code Optimization as a Side Effect of Instruction Scheduling	Rajiv Gupta	-\|\|-	-\|\|-
FP-Map - An Approach to the Functional Pipelining of Embedded Programs	Ireneusz Karkowski, Henk Corporaal	-\|\|-	-\|\|-
MINI-PANEL SESSION: Has Exploitable ILP Reached a Piont of Diminishing Returns?	Various	-\|\|-	-\|\|-

3^rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97)
http://www.
The Impact of ILP on Multiprocessor Performance and Simulation Methodology	Vijay S. Pai Parthasarathy Ranganathans Sarita V. Adve	-\|\|-	-\|\|-
Multiple Branch and Block Prediction	Steven Wallace Nader Bagherzadeh	-\|\|-	-\|\|-
Advances of the Counterflow Pipeline Microarchitecture	Kenneth J. Janik Shih-Lien Lu Michael F. Miller	-\|\|-	-\|\|-
Multithreaded Vector Architectures	Roger Espasa Mateo Valero	-\|\|-	-\|\|-
A Framework for Statistical Modeling of Superscalar Processor Performance	Derek B. Noonburg John Paul Shen	-\|\|-	-\|\|-
Control Flow Speculation in Multiscalar Processors	Quinn Jacobson Steve Bennett Nikhill Sharma James E. Smith

Yale Patt Papers
http://www.eecs.umich.edu/
Title	*Authors*	*Date*	*Published*
The Effects of Mispredicted-Path Execution on Branch Prediction Structures	Stephen Jourdan Tse-Hao Hsing Jared Stark Yale N. Patt	10/96	Proceedings of the 1996 Conference on Parallel Arhcitectures and Compilation Techniques - PACT 96
Using Predicated Execution to Improve the Performance of a Dynamically Scheduled Machine with Speculative Execution	Po-Yung Chang Eric Hao Yale N. Patt Pohua P. Chang		PACT 95
Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches	Marius Evers Po-Yung Chang Yale N. Patt		ISCA 23
Target Prediction for Indirect Jumps	Po-Yung Chang Eric Hao Yale N. Patt		ISCA 24
The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference	Eric Sprangle Robert S. Chappell Mitch Alsup Yale N. Patt		ISCA 24
Branch Clasification: A New Mechanism for Improving Branch Predictor Performance	Po-Yung Chang Eric Hao Tse-Yu Yeh Yale N. Patt		MICRO 27
The Effect of Speculatively Updating Branch History on Branch Prediction Accuarcy, Revisited	Eric Hao Po-Yung Chang Yale N. Patt		MICRO 27
Increasing the Instruction Fetch Rate via Multiple Branch Prediction and a Branch Address Cache	Tse-Yu Yeh Deborah T. Marr Yale N. Patt	07/93	7^th ACM International Conference on Supercomputing
Alternative Implementations of Hybrid Branch Predictors	Po-Yung Chang Eric Hao Yale N. Patt		MICRO 28

Dave Pattersson Papers
http://iram.cs.berkeley.edu/
Title	*Authors*	*Date*	*Published*
A Case for Intelligent RAM: IRAM	David Patterson Thomas Anderson Neal Cardwell Richard Fromm Kimberley Keeton Christoforos Kozyrakis Randi Thomas Katherine Yelick	1997	IEEE Micro April 1997
Intelligent RAM (IRAM): the Industrial Setting, Application, and Architectures	David Patterson Krste Asanovic Aaron Brown Richard Fromm Jason Golbus Benjamin Gribstad Kimberley Keeton Christoforos Kozyrakis David Martin Stylianos Perissakis Randi Thomas Noah Treuhaft Katherine Yelick	1997	ICDD 1997
The Energy Efficiency of IRAM Architectures	Richard Fromm Stylianos Perissakis Neal Cardwell Christoforos Kozyrakis Bruce McGauphy David Patterson Tom Anderson Katherine Yelick	1997	ISCA 1997
Evaluation of Existing Architectures in IRAM Systems	Ngeci Bowman Neal Cardwell Christoforos Kozyrakis Cynthia Romer Helen Wang	1997	Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97, Denver, CO, 1 June 1997.
IRAM and SmartSIMM: Overcoming the I/O Bus Bottleneck	Kimberley Keeton Remzi Arpaci-Dusseau David Patterson	1997	Workshop on Mixing Logic and DRAM: Chips that Compute and Remember at ISCA '97, Denver, CO, 1 June 1997

3^rd IEEE International Workshop on Rapid System Prototyping, Research Triangle Park, NC, June 1992.
http://www.
Systematic Prototyping of Superscalar Computer Architectures	Thomas M. Conte	1992

IEEE First International Conference on Algorithms and Architectures for Parallel Processing (ICA³PP ), Brisbane, Australia, April 1921, 1995
http://www.
BlockLevel Prediction for WideIssue Superscalar Processors	Simonjit Dutta Manoj Franklin	1995	f.icapp

International Conference on Parallel Processing, Aug, 11-15, 1997, Bloomingdale, Illinois
http://www.
Multiscalar Execution Along a Single Flow of Control	Krishna K. Sundararman Manoj Franklin	1997	Proceedings

PhD THESSIS
Data Preload For Superscalar nd VLIW Processors	William Yu-Wei Chen	1993	Univ.Illinois Urbana Champaign
Data Relocation and Prefetching for Programs with Large Sets	Yoyi Yamada	1995	Univ.Illinois Urbana Champaign
Speculative Execution based on Value Prediction	Freddy Gabbay	1996	Technion Israel Institute of Tech. EE
Memory-System Design Considerations for Dynamically-Scheduled Microprocessors	Keith Istvan Farkas	1997	ECE Univ. of Toronto
Support for Speculative Execution in High-Performance Processors	Michael David Smith	Nov. 1992	Stanford University

MS THESSIS
A Multiported Nonblocking Cache for a Superscalar Uniprocessor	James Edward Sicolo	1992	Univ.Illinois Urbana Champaign

MICRO XX, 1985
Critical Issues Regarding HPS, A High Peformance Microarchitecture	Y.N.Patt S.W.Melvin W.W.Hwu M.Shebanow	Dec.1985	Proc. 18th Annual Workshop on Microprogramming, Pacific Groove, CA, pp.109-116

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